Packages

package lib

Linear Supertypes
Scan, LowPrecision, LinearAlgebra, AnyRef, Any
Content Hierarchy
CMatrix[T]CVector[T]CScalar[T]BoxedC[T]MLHostML
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. lib
  2. Scan
  3. LowPrecision
  4. LinearAlgebra
  5. AnyRef
  6. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. All

Type Members

  1. trait HostML extends AnyRef
  2. trait LinearAlgebra extends AnyRef
  3. sealed abstract class BoxedC[T] extends AnyRef
    Definition Classes
    LinearAlgebra
  4. case class CMatrix[T](c: dsl.SRAM2[T]) extends BoxedC[T] with Product with Serializable
    Definition Classes
    LinearAlgebra
  5. case class CScalar[T](c: T) extends BoxedC[T] with Product with Serializable
    Definition Classes
    LinearAlgebra
  6. case class CVector[T](c: dsl.SRAM1[T]) extends BoxedC[T] with Product with Serializable
    Definition Classes
    LinearAlgebra
  7. trait LowPrecision extends AnyRef
  8. trait Scan extends AnyRef

Value Members

  1. def ConvertTo8Bit(Y: dsl.DRAM1[dsl.Byte], SF: dsl.Reg[dsl.Float], X: dsl.DRAM1[dsl.Float], size: dsl.Int): dsl.Unit
    Definition Classes
    LowPrecision
  2. def ConvertTo8Bit_Buggy(Y: dsl.DRAM1[dsl.Byte], SF: dsl.Reg[dsl.Float], X: dsl.DRAM1[dsl.Float], size: dsl.Int): dsl.Unit
    Definition Classes
    LowPrecision
  3. def addlp[T1, T2, OT](parent: dsl.Label, Y: dsl.SRAM2[OT], YSF: dsl.Reg[dsl.Float], X1: dsl.SRAM2[T1], X1SF: dsl.Reg[dsl.Float], X2: dsl.SRAM1[T2], X2SF: dsl.Reg[dsl.Float], transX2: Boolean, precision: Int, factor: Int)(implicit arg0: dsl.Num[T1], arg1: dsl.Num[T2], arg2: dsl.Num[OT], ctx: SrcCtx, state: State): dsl.Unit
    Definition Classes
    LowPrecision
  4. def averagepool2d[T](Y: dsl.SRAM4[T], X: dsl.SRAM4[T], kernel: (dsl.Int, dsl.Int), pad: (dsl.Int, dsl.Int, dsl.Int, dsl.Int), stride: (dsl.Int, dsl.Int))(implicit arg0: Type[T], arg1: dsl.Num[T], state: State): dsl.Unit
    Definition Classes
    LinearAlgebra
  5. def batchNorm2d[T](Y: dsl.SRAM4[T], X: dsl.SRAM4[T], scale: T, B: T, epsilon: dsl.Float)(implicit arg0: dsl.Num[T], state: State): dsl.Unit
    Definition Classes
    LinearAlgebra
  6. def batchNorm2d[T](Y: dsl.SRAM4[T], X: dsl.SRAM4[T], scale: dsl.SRAM1[T], B: dsl.SRAM1[T], epsilon: dsl.Float)(implicit arg0: dsl.Num[T], state: State): dsl.Unit
    Definition Classes
    LinearAlgebra
  7. def conv2d[T](Y: dsl.SRAM4[T], X: dsl.SRAM4[T], K: dsl.SRAM4[T], pad: (dsl.Int, dsl.Int), stride: (dsl.Int, dsl.Int))(implicit arg0: dsl.Num[T], state: State): dsl.Unit
    Definition Classes
    LinearAlgebra
  8. def dequant[T](parent: dsl.Label, Y: dsl.SRAM2[dsl.Float], SF: dsl.Reg[dsl.Float], X: dsl.SRAM2[T])(implicit arg0: dsl.Num[T], ctx: SrcCtx, state: State): dsl.Unit
    Definition Classes
    LowPrecision
  9. def filter[T](Y: dsl.SRAM1[T], P: (T) ⇒ dsl.Boolean, X: dsl.SRAM1[T])(implicit arg0: dsl.Num[T], ctx: SrcCtx, state: State): dsl.Unit
    Definition Classes
    Scan
  10. def filter_fifo[T](Y: dsl.SRAM1[T], P: (T) ⇒ dsl.Boolean, X: dsl.SRAM1[T], YS: dsl.Reg[dsl.Int])(implicit arg0: dsl.Num[T], ctx: SrcCtx, state: State): dsl.Unit
    Definition Classes
    Scan
  11. def gemm[T](Y: dsl.SRAM2[T], A: dsl.SRAM2[T], B: dsl.SRAM2[T], C: dsl.SRAM2[T], transA: Boolean, transB: Boolean, transY: Boolean, sumY: Boolean, alpha: T, beta: T, mp: Int, kp: Int, np: Int)(implicit arg0: dsl.Num[T], state: State): dsl.Unit
    Definition Classes
    LinearAlgebra
  12. def gemm[T](Y: dsl.SRAM2[T], A: dsl.SRAM2[T], B: dsl.SRAM2[T], C: dsl.SRAM1[T], transA: Boolean, transB: Boolean, transY: Boolean, sumY: Boolean, alpha: T, beta: T, mp: Int, kp: Int, np: Int)(implicit arg0: dsl.Num[T], state: State): dsl.Unit
    Definition Classes
    LinearAlgebra
  13. def gemm[T](Y: dsl.SRAM2[T], A: dsl.SRAM2[T], B: dsl.SRAM2[T], C: T, transA: Boolean, transB: Boolean, transY: Boolean, sumY: Boolean, alpha: T, beta: T, mp: Int, kp: Int, np: Int)(implicit arg0: dsl.Num[T], state: State): dsl.Unit
    Definition Classes
    LinearAlgebra
  14. def gemm_fpga_fix[T](Y: dsl.SRAM2[T], A: dsl.SRAM2[T], B: dsl.SRAM2[T], C: T, transA: Boolean, transB: Boolean, transY: Boolean, sumY: Boolean, alpha: T, beta: T, mp: Int = 1, kp: Int = 1, np: Int = 1)(implicit arg0: dsl.Num[T], state: State): dsl.Unit
    Definition Classes
    LinearAlgebra
  15. def matmult[T](Y: dsl.SRAM2[T], A: dsl.SRAM2[T], B: dsl.SRAM2[T], transA: Boolean, transB: Boolean, transY: Boolean, mp: Int = 1, kp: Int = 1, np: Int = 1)(implicit arg0: dsl.Num[T], state: State): dsl.Unit
    Definition Classes
    LinearAlgebra
  16. def maxpool2d[T](Y: dsl.SRAM4[T], X: dsl.SRAM4[T], kernel: (dsl.Int, dsl.Int), pad: (dsl.Int, dsl.Int, dsl.Int, dsl.Int), stride: (dsl.Int, dsl.Int))(implicit arg0: dsl.Num[T], state: State): dsl.Unit
    Definition Classes
    LinearAlgebra
  17. def mmlp[IT, OT](parent: dsl.Label, Y: dsl.SRAM2[OT], YSF: dsl.Reg[dsl.Float], A: dsl.SRAM2[IT], ASF: dsl.Reg[dsl.Float], B: dsl.SRAM2[IT], BSF: dsl.Reg[dsl.Float], transA: Boolean, transB: Boolean, transY: Boolean)(implicit arg0: dsl.Num[IT], arg1: dsl.Num[OT], ctx: SrcCtx, state: State): dsl.Unit
    Definition Classes
    LowPrecision
  18. def quantize[T](parent: dsl.Label, Y: dsl.SRAM1[T], SF: dsl.Reg[dsl.Float], X: dsl.SRAM1[dsl.Float], factor: Int, precision: Int)(implicit arg0: dsl.Num[T], ctx: SrcCtx, state: State): dsl.Unit
    Definition Classes
    LowPrecision
  19. def quantize[T](parent: dsl.Label, Y: dsl.SRAM2[T], SF: dsl.Reg[dsl.Float], X: dsl.SRAM2[dsl.Float], factor: Int, precision: Int)(implicit arg0: dsl.Num[T], ctx: SrcCtx, state: State): dsl.Unit
    Definition Classes
    LowPrecision
  20. def testmem(Y: dsl.DRAM1[dsl.Float], X: dsl.DRAM1[dsl.Float], size: dsl.Int): dsl.Unit
    Definition Classes
    LowPrecision
  21. def testreg(Z: dsl.Reg[dsl.Float], Y: dsl.Reg[dsl.Float], X: dsl.Reg[dsl.Float]): dsl.Unit
    Definition Classes
    LowPrecision
  22. object BLAS
  23. object ML extends HostML
  24. object Sort

Inherited from Scan

Inherited from LowPrecision

Inherited from LinearAlgebra

Inherited from AnyRef

Inherited from Any

Ungrouped