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object XilinxDevice

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  1. final def !=(arg0: Any): Boolean
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  2. final def ##(): Int
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  3. final def ==(arg0: Any): Boolean
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  4. val BRAM: String
  5. val DSPs: String
  6. val LUT1: String
  7. val LUT2: String
  8. val LUT3: String
  9. val LUT4: String
  10. val LUT5: String
  11. val LUT6: String
  12. val LUTs: List[String]
  13. val MUX7: String
  14. val MUX8: String
  15. val Mregs: String
  16. val RAM128X1D: String
  17. val RAM128X1S: String
  18. val RAM18: String
  19. val RAM256X1S: String
  20. val RAM32M: String
  21. val RAM32X1D: String
  22. val RAM32X1S: String
  23. val RAM36: String
  24. val RAM64M: String
  25. val RAM64X1D: String
  26. val RAM64X1S: String
  27. val RAM_LUT_USAGE: Map[String, Int]
  28. val RAMs: List[String]
  29. val Regs: String
  30. val SLICEL: String
  31. val SLICEM: String
  32. val SRL16E: String
  33. val SRLC32E: String
  34. val Slices: String
  35. val URAM: String
  36. final def asInstanceOf[T0]: T0
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  37. def clone(): AnyRef
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  38. final def eq(arg0: AnyRef): Boolean
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  39. def equals(arg0: Any): Boolean
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  40. def finalize(): Unit
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  41. final def getClass(): Class[_]
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  42. def hashCode(): Int
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  43. final def isInstanceOf[T0]: Boolean
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  44. final def ne(arg0: AnyRef): Boolean
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  45. final def notify(): Unit
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  46. final def notifyAll(): Unit
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  47. final def synchronized[T0](arg0: ⇒ T0): T0
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  48. def toString(): String
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  49. final def wait(): Unit
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